library ieee;
use ieee.std_logic_1164.all;
 
entity at is
port (
      temp_sensor	:in INTEGER;               -- up_down control for counter
      power_button	:in std_logic;
      speed_button	:in std_logic;
      temp_setting	:in INTEGER;
      clk		:in  std_logic;                   -- Input clock
      reset		:in  std_logic;                   -- Input reset
      compressor	:out std_logic;
      high_speed	:out std_logic;
      low_speed		:out std_logic;
      power_led		:out std_logic;
      high_speed_led	:out std_logic;
      low_speed_led	:out std_logic    

);
end entity;
 
architecture rtl of at is
	signal comp	:std_logic;
	signal h_s	:std_logic;
	signal l_s	:std_logic;
  signal pwr_led :std_logic;
	begin
		process (clk, reset) begin
			if (reset = '1') then
				comp 	<= '0';
				h_s 	<= '0';
				l_s 	<= '0';
			elsif (rising_edge(clk)) then
				if (power_button = '1') then
					comp <= '1';
				else
					comp <= '0';
					pwr_led <= '0';
				end if;
			end if;
		end process;
		compressor 	<= comp;
		high_speed 	<= h_s;
		low_speed	<= l_s;
    power_led <= pwr_led;
end architecture;